1. Field of the Invention
The present invention relates to a data processing apparatus that allows lower power consumption in a system for controlling a resource having an AC parameter, such as a nonvolatile semiconductor memory, without reducing the performance of access to the resource, by reducing the frequency of a system clock signal while requesting access to the resource.
2. Description of the Related Art
For memory devices, such as a Synchronous Dynamic Random Access Memory (SDRAM) and the like, a time constraint on an interval between each command in a command control for access is defined as an AC parameter. This AC parameter is defined in terms of time. However, since a circuit for controlling a memory device is operated with reference to a clock signal, the circuit generally converts the AC parameter into the number of clock cycles and performs a control using the number of clock cycles.
In a system including an SDRAM, when the clock frequency of the system is reduced so as to achieve lower power consumption or when the clock frequency is increased so as to achieve an operation in a high-speed mode, the number of clock cycles obtained by conversion of the AC parameter differs between before and after the changing of the clock frequency, so that the number of clock cycles also needs be changed, depending on the change in the clock frequency. In this case, a complicated circuit configuration is required so as to change the number of clock cycles when a memory device is being accessed. Therefore, it is necessary to temporarily stop access to the memory device so as to change the number of clock cycles.
According to a conventional technique, a processor stops access to a memory device, confirms the stop of an operation of another access master, such as a Direct Memory Access Controller (DMAC) or the like, using software, and changes the set number of clock cycles, and thereafter, instructs a clock control section to change the clock frequency, and resumes access to the memory device after confirmation of the change of the clock frequency, thereby making it possible to change the clock frequency (see Japanese Unexamined Patent Application Publication No. 2004-074623).